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[PATCH 04/10] tcg/s390x: Support MIE2 MGRK instruction
From: |
Richard Henderson |
Subject: |
[PATCH 04/10] tcg/s390x: Support MIE2 MGRK instruction |
Date: |
Thu, 24 Feb 2022 05:43:27 -1000 |
The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 6 ++++++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 685739329e..fea73b6ed0 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -31,6 +31,7 @@ C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0)
C_O2_I2(b, a, 0, r)
+C_O2_I2(b, a, r, r)
C_O2_I3(b, a, 0, 1, r)
C_O2_I4(r, r, 0, 1, rA, r)
C_O2_I4(r, r, 0, 1, ri, r)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index a625ef63ac..280e752d94 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -136,7 +136,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
-#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2)
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index ab92a2a82c..77d7bb6cf5 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -186,6 +186,7 @@ typedef enum S390Opcode {
RRE_SLBGR = 0xb989,
RRE_XGR = 0xb982,
+ RRFa_MGRK = 0xb9ec,
RRFa_MSRKC = 0xb9fd,
RRFa_MSGRKC = 0xb9ed,
RRFa_NRK = 0xb9f4,
@@ -2547,6 +2548,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
case INDEX_op_mulu2_i64:
tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
break;
+ case INDEX_op_muls2_i64:
+ tcg_out_insn(s, RRFa, MGRK, TCG_REG_R2, args[2], args[3]);
+ break;
case INDEX_op_shl_i64:
op = RSY_SLLG;
@@ -3235,6 +3239,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_mulu2_i64:
return C_O2_I2(b, a, 0, r);
+ case INDEX_op_muls2_i64:
+ return C_O2_I2(b, a, r, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
--
2.25.1
- [PATCH 00/10] tcg/s390x: updates for mie2 and mie3, Richard Henderson, 2022/02/24
- [PATCH 01/10] tcg/s390x: Distinguish RRF-a and RRF-c formats, Richard Henderson, 2022/02/24
- [PATCH 02/10] tcg/s390x: Distinguish RIE formats, Richard Henderson, 2022/02/24
- [PATCH 03/10] tcg/s390x: Support MIE2 multiply single instructions, Richard Henderson, 2022/02/24
- [PATCH 06/10] tcg/s390x: Create tgen_cmp2 to simplify movcond, Richard Henderson, 2022/02/24
- [PATCH 05/10] tcg/s390x: Support MIE3 logical operations, Richard Henderson, 2022/02/24
- [PATCH 04/10] tcg/s390x: Support MIE2 MGRK instruction,
Richard Henderson <=
- [PATCH 08/10] tcg/s390x: Use tgen_movcond_int in tgen_clz, Richard Henderson, 2022/02/24
- [PATCH 07/10] tcg/s390x: Support SELGR instruction in MOVCOND, Richard Henderson, 2022/02/24
- [PATCH 09/10] tcg/s390x: Use vector ctz for integer ctz, Richard Henderson, 2022/02/24
- [PATCH 10/10] tcg/s390x: Implement ctpop operation, Richard Henderson, 2022/02/24