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[PATCH v3 09/26] s390x/tcg: Simplify vflr64() handling
From: |
David Hildenbrand |
Subject: |
[PATCH v3 09/26] s390x/tcg: Simplify vflr64() handling |
Date: |
Mon, 7 Jun 2021 13:03:21 +0200 |
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 -
target/s390x/translate_vx.c.inc | 3 +--
target/s390x/vec_fpu_helper.c | 29 +++++++----------------------
3 files changed, 8 insertions(+), 25 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 63039c8d73..0cfb82ee8a 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -263,7 +263,6 @@ DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr,
cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
-DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr,
env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index 5ff59984b5..91e2967c49 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2531,7 +2531,6 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
const uint8_t fpf = get_field(s, m3);
const uint8_t m4 = get_field(s, m4);
const uint8_t erm = get_field(s, m5);
- const bool se = extract32(m4, 3, 1);
gen_helper_gvec_2_ptr *fn;
if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) {
@@ -2556,7 +2555,7 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
fn = gen_helper_gvec_vfi64;
break;
case 0xc5:
- fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64;
+ fn = gen_helper_gvec_vflr64;
break;
default:
g_assert_not_reached();
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 7bd3e44acc..7ca9c892f7 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -311,9 +311,12 @@ void HELPER(gvec_vfll32)(void *v1, const void *v2,
CPUS390XState *env,
*(S390Vector *)v1 = tmp;
}
-static void vflr64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
- bool s, bool XxC, uint8_t erm, uintptr_t retaddr)
+void HELPER(gvec_vflr64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool s = extract32(simd_data(desc), 3, 1);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
uint8_t vxc, vec_exc = 0;
S390Vector tmp = {};
int i, old_mode;
@@ -332,26 +335,8 @@ static void vflr64(S390Vector *v1, const S390Vector *v2,
CPUS390XState *env,
}
}
s390_restore_bfp_rounding_mode(env, old_mode);
- handle_ieee_exc(env, vxc, vec_exc, retaddr);
- *v1 = tmp;
-}
-
-void HELPER(gvec_vflr64)(void *v1, const void *v2, CPUS390XState *env,
- uint32_t desc)
-{
- const uint8_t erm = extract32(simd_data(desc), 4, 4);
- const bool XxC = extract32(simd_data(desc), 2, 1);
-
- vflr64(v1, v2, env, false, XxC, erm, GETPC());
-}
-
-void HELPER(gvec_vflr64s)(void *v1, const void *v2, CPUS390XState *env,
- uint32_t desc)
-{
- const uint8_t erm = extract32(simd_data(desc), 4, 4);
- const bool XxC = extract32(simd_data(desc), 2, 1);
-
- vflr64(v1, v2, env, true, XxC, erm, GETPC());
+ handle_ieee_exc(env, vxc, vec_exc, GETPC());
+ *(S390Vector *)v1 = tmp;
}
static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
--
2.31.1
- [PATCH v3 00/26] s390x/tcg: Implement Vector enhancements facility and switch to z14, David Hildenbrand, 2021/06/07
- [PATCH v3 01/26] s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling, David Hildenbrand, 2021/06/07
- [PATCH v3 02/26] s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED), David Hildenbrand, 2021/06/07
- [PATCH v3 03/26] s390x/tcg: Simplify vop64_3() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 04/26] s390x/tcg: Simplify vop64_2() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 05/26] s390x/tcg: Simplify vfc64() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 06/26] s390x/tcg: Simplify vftci64() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 07/26] s390x/tcg: Simplify vfma64() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 08/26] s390x/tcg: Simplify vfll32() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 09/26] s390x/tcg: Simplify vflr64() handling,
David Hildenbrand <=
- [PATCH v3 10/26] s390x/tcg: Simplify wfc64() handling, David Hildenbrand, 2021/06/07
- [PATCH v3 11/26] s390x/tcg: Implement VECTOR BIT PERMUTE, David Hildenbrand, 2021/06/07
- [PATCH v3 12/26] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL, David Hildenbrand, 2021/06/07
- [PATCH v3 13/26] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT), David Hildenbrand, 2021/06/07
- [PATCH v3 14/26] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT), David Hildenbrand, 2021/06/07
- [PATCH v3 15/26] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *, David Hildenbrand, 2021/06/07
- [PATCH v3 16/26] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, David Hildenbrand, 2021/06/07
- [PATCH v3 17/26] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED, David Hildenbrand, 2021/06/07
- [PATCH v3 18/26] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED, David Hildenbrand, 2021/06/07
- [PATCH v3 19/26] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION, David Hildenbrand, 2021/06/07