Re: [PATCH v1 2/5] s390x/mmu: Implement ESOP-2 and access-exception-fetch/store-indication facility

[Thomas Huth]

On 27/09/2019 14.30, David Hildenbrand wrote:
> On 26.09.19 12:16, David Hildenbrand wrote:
>> We already implement ESOP-1. For ESOP-2, we only have to indicate all
>> protection exceptions properly. Due to EDAT-1, we already indicate DAT
>> exceptions properly. We don't trigger KCP/ALCP/IEP exceptions yet.
>>
>> So all we have to do is set the TEID (TEC) to the right values
>> (bit 56, 60, 61) in case of LAP.
>>
>> We don't have any side-effects (e.g., no guarded-storage facility),
>> therefore, bit 64 of the TEID (TEC) is always 0.
>>
>> We always have to indicate whether it is a fetch or a store for all access
>> exceptions. This is only missing for LAP exceptions.
>>
>> Signed-off-by: David Hildenbrand <address@hidden>
>> ---
>>  target/s390x/mmu_helper.c | 12 ++++++++++--
>>  1 file changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
>> index 54f54137ec..8abc5d31d8 100644
>> --- a/target/s390x/mmu_helper.c
>> +++ b/target/s390x/mmu_helper.c
>> @@ -384,7 +384,9 @@ int mmu_translate(CPUS390XState *env, target_ulong 
>> vaddr, int rw, uint64_t asc,
>>          *flags |= PAGE_WRITE_INV;
>>          if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
>>              if (exc) {
>> -                trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
>> +                /* LAP sets bit 56 */
>> +                tec |= 0x80;
>> +                trigger_access_exception(env, PGM_PROTECTION, ilen, tec);
>>              }
>>              return -EACCES;
>>          }
>> @@ -540,6 +542,10 @@ void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, 
>> uintptr_t ra)
>>  int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
>>                         target_ulong *addr, int *flags)
>>  {
>> +    /* Code accesses have an undefined ilc, let's use 2 bytes. */
>> +    const int ilen = (rw == MMU_INST_FETCH) ? 2 : ILEN_AUTO;
>> +    uint64_t tec = (raddr & TARGET_PAGE_MASK) |
>> +                   (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
>>      const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
>>  
>>      *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>> @@ -547,7 +553,9 @@ int mmu_translate_real(CPUS390XState *env, target_ulong 
>> raddr, int rw,
>>          /* see comment in mmu_translate() how this works */
>>          *flags |= PAGE_WRITE_INV;
>>          if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
>> -            trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0);
>> +            /* LAP sets bit 56 */
>> +            tec |= 0x80;
>> +            trigger_access_exception(env, PGM_PROTECTION, ilen, tec);
> 
> I'll drop the ilen change from this patch again as it is handled
> properly when filling the TLB and Richard is about to rework that either
> way.
> 

Acked-by: Thomas Huth <address@hidden>