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Re: [qemu-s390x] [Qemu-devel] [PATCH v1 08/33] s390x/tcg: Implement VECT
From: |
Richard Henderson |
Subject: |
Re: [qemu-s390x] [Qemu-devel] [PATCH v1 08/33] s390x/tcg: Implement VECTOR LOAD |
Date: |
Wed, 27 Feb 2019 07:39:47 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 2/26/19 3:38 AM, David Hildenbrand wrote:
> +static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
> +{
> + load_vec_element(s, TMP_VREG_0, 0, o->addr1, MO_64);
> + gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
> + load_vec_element(s, TMP_VREG_0, 1, o->addr1, MO_64);
> + gen_gvec_mov(get_field(s->fields, v1), TMP_VREG_0);
> + return DISAS_NEXT;
> +}
Isn't it just as easy to load two TCGv_i64 temps and store into the correct
vector afterward?
Also, it is easy to honor the required alignment:
TCGMemOp mop1, mop2;
if (m3 < 3) {
mop1 = mop2 = MO_TEQ;
} else if (m3 == 3) {
mop1 = mop2 = MO_TEQ | MO_ALIGN;
} else {
mop1 = MO_TEQ | MO_ALIGN_16;
mop2 = MO_TEQ | MO_ALIGN;
}
tcg_gen_qemu_ld_i64(tmp1, o->addr1, mem_idx, mop1);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
tcg_gen_qemu_ld_i64(tmp2, o->addr1, mem_idx, mop2);
write_vec_element_i64(tmp1, v1, 0, MO_64);
write_vec_element_i64(tmp2, v1, 1, MO_64);
r~
[qemu-s390x] [PATCH v1 05/33] s390x/tcg: Implement VECTOR GATHER ELEMENT, David Hildenbrand, 2019/02/26
[qemu-s390x] [PATCH v1 12/33] s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT, David Hildenbrand, 2019/02/26
[qemu-s390x] [PATCH v1 20/33] s390x/tcg: Implement VECTOR PACK, David Hildenbrand, 2019/02/26