[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 1/5] target/riscv: Add svukte extension capability variable
From: |
Fea.Wang |
Subject: |
[PATCH 1/5] target/riscv: Add svukte extension capability variable |
Date: |
Tue, 3 Sep 2024 14:17:53 +0800 |
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 96fe26d4ea..636b12e1c2 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -81,6 +81,7 @@ struct RISCVCPUConfig {
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
--
2.34.1
- [PATCH 0/5] Introduce svukte ISA extension, Fea.Wang, 2024/09/03
- [PATCH 1/5] target/riscv: Add svukte extension capability variable,
Fea.Wang <=
- [PATCH 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Fea.Wang, 2024/09/03
- [PATCH 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Fea.Wang, 2024/09/03
- [PATCH 4/5] target/riscv: Check memory access to meet svuket rule, Fea.Wang, 2024/09/03
- [PATCH 5/5] target/riscv: Expose svukte ISA extension, Fea.Wang, 2024/09/03
- Re: [PATCH 0/5] Introduce svukte ISA extension, Alistair Francis, 2024/09/03