Re: [PATCH v2 05/14] tcg/riscv: Implement vector load/store

[Richard Henderson]

On 8/30/24 16:15, LIU Zhiwei wrote:
> @@ -799,6 +834,17 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, 
> TCGReg data,
>       case OPC_SD:
>           tcg_out_opc_store(s, opc, addr, data, imm12);
>           break;
> +    case OPC_VSE8_V:
> +    case OPC_VSE16_V:
> +    case OPC_VSE32_V:
> +    case OPC_VSE64_V:
> +    case OPC_VS1R_V:
> +    case OPC_VS2R_V:
> +    case OPC_VS4R_V:
> +    case OPC_VS8R_V:
> +        tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, imm12);
> +        tcg_out_opc_ldst_vec(s, opc, data, TCG_REG_TMP0, true);
> +        break;
>       case OPC_LB:
>       case OPC_LBU:
>       case OPC_LH:

I think you shouldn't try to handle vector load/store in this same function.
You'll want something like

    if (offset != 0) {
        if (offset == sextreg(offset, 12)) {
            tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, offset);
        } else {
            tcg_out_movi(s, TCG_REG_TMP0, offset);
            tcg_out_opc_reg(s, TCG_REG_TMP0, TCG_REG_TMP0, addr);
        }
        addr = TCG_REG_TMP0;
    }

at the top, instead of the imm12 split currently at the top of tcg_out_ldst.


r~