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[PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU |
Date: |
Wed, 3 Jul 2024 20:34:42 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
v2:
Remove the line that was inadvertently left in PATCH v1 4/6.
Add an avocado test.
v1:
https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
TANG Tiancheng (7):
target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Enable RV32 CPU support in RV64 QEMU
tests/avocado: Add an avocado test for riscv64
configs/targets/riscv64-softmmu.mak | 2 +-
hw/riscv/boot.c | 35 +++++++++++++++++++----------
hw/riscv/sifive_u.c | 3 ++-
include/hw/riscv/boot.h | 4 +++-
include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++++
target/riscv/cpu.c | 17 ++++++++++----
target/riscv/cpu.h | 5 ++++-
target/riscv/cpu_helper.c | 25 +++++++++++++++------
target/riscv/pmp.c | 2 +-
tests/avocado/boot_linux_console.py | 35 +++++++++++++++++++++++++++++
10 files changed, 129 insertions(+), 28 deletions(-)
--
2.43.0
- [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU,
LIU Zhiwei <=
- [PATCH v2 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, LIU Zhiwei, 2024/07/03
- [PATCH v2 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32, LIU Zhiwei, 2024/07/03
- [PATCH v2 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v2 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64, LIU Zhiwei, 2024/07/03
- [PATCH v2 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v2 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v2 7/7] tests/avocado: Add an avocado test for riscv64, LIU Zhiwei, 2024/07/03
- Re: [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU, Philippe Mathieu-Daudé, 2024/07/03