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[PATCH] target/riscv/cpu.h: mcountinhibit, mcounteren and scounteren alw
From: |
Vadim Shakirov |
Subject: |
[PATCH] target/riscv/cpu.h: mcountinhibit, mcounteren and scounteren always 32-bit |
Date: |
Wed, 24 Jan 2024 15:06:58 +0300 |
mcountinhibit, mcounteren and scounteren must always be 32-bit by
privileged spec
Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
---
target/riscv/cpu.h | 6 +++---
target/riscv/machine.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b0824ef8f..3cf059199c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,10 +317,10 @@ struct CPUArchState {
*/
bool two_stage_indirect_lookup;
- target_ulong scounteren;
- target_ulong mcounteren;
+ uint32_t scounteren;
+ uint32_t mcounteren;
- target_ulong mcountinhibit;
+ uint32_t mcountinhibit;
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index fdde243e04..daab121799 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -398,9 +398,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mtval, RISCVCPU),
VMSTATE_UINTTL(env.miselect, RISCVCPU),
VMSTATE_UINTTL(env.siselect, RISCVCPU),
- VMSTATE_UINTTL(env.scounteren, RISCVCPU),
- VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
- VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
+ VMSTATE_UINT32(env.scounteren, RISCVCPU),
+ VMSTATE_UINT32(env.mcounteren, RISCVCPU),
+ VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState),
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
--
2.34.1
- [PATCH] target/riscv/cpu.h: mcountinhibit, mcounteren and scounteren always 32-bit,
Vadim Shakirov <=