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[PATCH 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator |
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Date: |
Tue, 27 Jun 2023 01:19:55 +0200 |
We only build for 32/64-bit hosts, so TCG is required for
128-bit targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 175dbc9826..7f281cdcf6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -473,6 +473,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
#endif
}
+#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
if (qemu_tcg_mttcg_enabled()) {
@@ -491,7 +492,10 @@ static void rv128_base_cpu_init(Object *obj)
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
}
-#else
+#endif
+
+#else /* !TARGET_RISCV64 */
+
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -573,7 +577,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
}
-#endif
+#endif /* !TARGET_RISCV64 */
#if defined(CONFIG_KVM)
static void riscv_host_cpu_init(Object *obj)
@@ -1947,8 +1951,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
+#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
-#endif
+#endif /* CONFIG_TCG */
+#endif /* TARGET_RISCV64 */
};
DEFINE_TYPES(riscv_cpu_type_infos)
--
2.38.1
- [PATCH 00/16] target/riscv: Allow building without TCG (KVM-only so far), Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 01/16] target/riscv: Remove unused 'instmap.h' header in translate.c, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 02/16] target/riscv: Restrict KVM-specific fields from ArchCPU, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 03/16] target/riscv: Restrict sysemu specific header to user emulation, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator,
Philippe Mathieu-Daudé <=
- [PATCH 05/16] target/riscv: Move sysemu-specific files to target/riscv/sysemu/, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 06/16] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 09/16] target/riscv: Expose some 'trigger' prototypes from debug.c, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 10/16] target/riscv: Extract TCG-specific code from debug.c, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 11/16] target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 12/16] target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c, Philippe Mathieu-Daudé, 2023/06/26
- [RFC PATCH 13/16] target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c, Philippe Mathieu-Daudé, 2023/06/26
- [PATCH 14/16] target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c, Philippe Mathieu-Daudé, 2023/06/26