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Re: [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are c
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed |
Date: |
Wed, 17 May 2023 12:12:33 +1000 |
On Sat, Apr 29, 2023 at 12:39 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> MMWP and MML bits may affect the allowed privs of PMP entries and the
> default privs, both of which may change the allowed privs of exsited
> TLB entries. So we need flush TLB when they are changed.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index d2d8429277..80889a1185 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -578,6 +578,9 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong
> val)
> if (riscv_cpu_cfg(env)->epmp) {
> /* Sticky bits */
> val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> + if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> + tlb_flush(env_cpu(env));
> + }
> } else {
> val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
> }
> --
> 2.25.1
>
>
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