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[PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instru
From: |
Weiwei Li |
Subject: |
[PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault |
Date: |
Thu, 30 Mar 2023 11:46:36 +0800 |
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc
b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c36..4b730cd492 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
static bool check_access(DisasContext *ctx)
{
if (!ctx->hlsx) {
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ offsetof(CPURISCVState, bins));
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
--
2.25.1
- [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault,
Weiwei Li <=