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[PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt()
From: |
Palmer Dabbelt |
Subject: |
[PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt() |
Date: |
Fri, 3 Mar 2023 00:37:28 -0800 |
From: Bin Meng <bmeng@tinylab.org>
Move the dtb load bits outside of create_fdt(), and put it explicitly
in sifive_u_machine_init() and virt_machine_init(). With such change
create_fdt() does exactly what its function name tells us.
Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230228074522.1845007-2-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
hw/riscv/sifive_u.c | 31 +++++++++++++++----------------
hw/riscv/virt.c | 29 ++++++++++++++---------------
include/hw/riscv/sifive_u.h | 1 +
3 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 76db5ed3dd..35a335b8d0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -99,7 +99,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
MachineState *ms = MACHINE(s);
uint64_t mem_size = ms->ram_size;
void *fdt;
- int cpu, fdt_size;
+ int cpu;
uint32_t *cells;
char *nodename;
uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
@@ -112,19 +112,10 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
"sifive,plic-1.0.0", "riscv,plic0"
};
- if (ms->dtb) {
- fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
- if (!fdt) {
- error_report("load_device_tree() failed");
- exit(1);
- }
- return;
- } else {
- fdt = ms->fdt = create_device_tree(&fdt_size);
- if (!fdt) {
- error_report("create_device_tree() failed");
- exit(1);
- }
+ fdt = ms->fdt = create_device_tree(&s->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
}
qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
@@ -561,8 +552,16 @@ static void sifive_u_machine_init(MachineState *machine)
qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
- /* create device tree */
- create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
+ /* load/create device tree */
+ if (machine->dtb) {
+ machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
+ if (!machine->fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ } else {
+ create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
+ }
if (s->start_in_flash) {
/*
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 981392c0bb..4f8191860b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1009,19 +1009,10 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap)
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
uint8_t rng_seed[32];
- if (ms->dtb) {
- ms->fdt = load_device_tree(ms->dtb, &s->fdt_size);
- if (!ms->fdt) {
- error_report("load_device_tree() failed");
- exit(1);
- }
- return;
- } else {
- ms->fdt = create_device_tree(&s->fdt_size);
- if (!ms->fdt) {
- error_report("create_device_tree() failed");
- exit(1);
- }
+ ms->fdt = create_device_tree(&s->fdt_size);
+ if (!ms->fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
}
qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
@@ -1506,8 +1497,16 @@ static void virt_machine_init(MachineState *machine)
}
virt_flash_map(s, system_memory);
- /* create device tree */
- create_fdt(s, memmap);
+ /* load/create device tree */
+ if (machine->dtb) {
+ machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
+ if (!machine->fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ } else {
+ create_fdt(s, memmap);
+ }
s->machine_done.notify = virt_machine_done;
qemu_add_machine_init_done_notifier(&s->machine_done);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 65af306963..0696f85942 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -68,6 +68,7 @@ typedef struct SiFiveUState {
/*< public >*/
SiFiveUSoCState soc;
+ int fdt_size;
bool start_in_flash;
uint32_t msel;
--
2.39.2
- [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair, (continued)
- [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair, Palmer Dabbelt, 2023/03/03
- [PULL 38/59] target/riscv: Allow debugger to access seed CSR, Palmer Dabbelt, 2023/03/03
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03
- [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03
- [PULL 45/59] target/riscv: Add support for Zicond extension, Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt(),
Palmer Dabbelt <=
- [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg, Palmer Dabbelt, 2023/03/03
- [PULL 50/59] target/riscv: Add csr support for svadu, Palmer Dabbelt, 2023/03/03
- [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 53/59] target/riscv: Export Svadu property, Palmer Dabbelt, 2023/03/03
- [PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- [PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s(), Palmer Dabbelt, 2023/03/03
- [PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers, Palmer Dabbelt, 2023/03/03
- [PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr(), Palmer Dabbelt, 2023/03/03
- [PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03