[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhi
From: |
Palmer Dabbelt |
Subject: |
[PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx |
Date: |
Fri, 3 Mar 2023 00:36:53 -0800 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
will be enabled when Zhinx is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-3-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a717f5d995..dcd85f7f27 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -754,8 +754,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
}
/* Set the ISA extensions, checks should have happened above */
- if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
- cpu->cfg.ext_zhinxmin) {
+ if (cpu->cfg.ext_zhinx) {
+ cpu->cfg.ext_zhinxmin = true;
+ }
+
+ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
cpu->cfg.ext_zfinx = true;
}
--
2.39.2
- [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Palmer Dabbelt, 2023/03/03
- [PULL 01/59] target/riscv: introduce riscv_cpu_cfg(), Palmer Dabbelt, 2023/03/03
- [PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Palmer Dabbelt, 2023/03/03
- [PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG, Palmer Dabbelt, 2023/03/03
- [PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP, Palmer Dabbelt, 2023/03/03
- [PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus(), Palmer Dabbelt, 2023/03/03
- [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx,
Palmer Dabbelt <=
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Palmer Dabbelt, 2023/03/03
- [PULL 03/59] target/riscv: allow MISA writes as experimental, Palmer Dabbelt, 2023/03/03
- [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP, Palmer Dabbelt, 2023/03/03
- [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends, Palmer Dabbelt, 2023/03/03
- [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU, Palmer Dabbelt, 2023/03/03
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh, Palmer Dabbelt, 2023/03/03
- [PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D, Palmer Dabbelt, 2023/03/03
- [PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Palmer Dabbelt, 2023/03/03
- [PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f, Palmer Dabbelt, 2023/03/03