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[PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues


From: Alistair Francis
Subject: [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues
Date: Wed, 14 Sep 2022 12:11:05 +0200

The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
ROM flow. This series makes it more configurguable from the command line
and fixes the default.

Alistair Francis (3):
  target/riscv: Set the CPU resetvec directly
  hw/riscv: opentitan: Fixup resetvec
  hw/riscv: opentitan: Expose the resetvec as a SoC property

 include/hw/riscv/opentitan.h |  2 ++
 target/riscv/cpu.h           |  3 +--
 hw/riscv/opentitan.c         |  8 +++++++-
 target/riscv/cpu.c           | 13 +++----------
 target/riscv/machine.c       |  6 +++---
 5 files changed, 16 insertions(+), 16 deletions(-)

-- 
2.37.2




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