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Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from p
From: |
Gerd Hoffmann |
Subject: |
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash |
Date: |
Tue, 6 Sep 2022 12:41:28 +0200 |
Hi,
> 3)Make the EDK2 image size to match with what qemu flash expects
> truncate -s 32M Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd
Hmm, we have that kind of padding on arm too (64M for code and 64M for
vars) and only a fraction of the space is actually used, which isn't
exactly ideal. So not sure it is a good plan to repeat that on riscv.
Also: Do you have support for persistent efi variables? If that is the
case then it makes sense to have separate pflash devices for code and
variable store. First because you can map the code part read-only then,
and second because decoupling code + vars to separate files allows easy
firmware code updates without loosing the variable store.
take care,
Gerd
[PATCH V4 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel, Sunil V L, 2022/09/06
[PATCH V4 3/3] hw/riscv: virt: Enable booting S-mode firmware from pflash, Sunil V L, 2022/09/06
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash,
Gerd Hoffmann <=