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Re: [PATCH v9 12/12] target/riscv: Update the privilege field for sscofp
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v9 12/12] target/riscv: Update the privilege field for sscofpmf CSRs |
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Date: |
Tue, 31 May 2022 10:12:16 +1000 |
On Tue, May 24, 2022 at 9:59 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The sscofpmf extension was ratified as a part of priv spec v1.12.
> Mark the csr_ops accordingly.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 90 ++++++++++++++++++++++++++++++----------------
> 1 file changed, 60 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e229f53c674d..c6105edd7a1a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -4012,63 +4012,92 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmevent },
>
> [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
> [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
>
> [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
> [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
> @@ -4158,7 +4187,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmcounterh },
> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> write_mhpmcounterh },
> - [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf },
> + [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf,
> + .min_priv_ver = PRIV_VERSION_1_12_0
> },
>
> #endif /* !CONFIG_USER_ONLY */
> };
> --
> 2.25.1
>
>
- [PATCH v9 03/12] target/riscv: pmu: Rename the counters extension to pmu, (continued)
- [PATCH v9 03/12] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2022/05/23
- [PATCH v9 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/05/23
- [PATCH v9 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/05/23
- [PATCH v9 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/05/23
- [PATCH v9 09/12] target/riscv: Simplify counter predicate function, Atish Patra, 2022/05/23
- [PATCH v9 11/12] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2022/05/23
- [PATCH v9 12/12] target/riscv: Update the privilege field for sscofpmf CSRs, Atish Patra, 2022/05/23
- Re: [PATCH v9 12/12] target/riscv: Update the privilege field for sscofpmf CSRs,
Alistair Francis <=
- [PATCH v9 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/05/23
- [PATCH v9 10/12] target/riscv: Add few cache related PMU events, Atish Patra, 2022/05/23