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Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec v
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From: |
Atish Patra |
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Subject: |
Re: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match |
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Date: |
Fri, 13 May 2022 11:45:14 -0700 |
On Wed, May 11, 2022 at 7:46 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should disable extensions in riscv_cpu_realize() if minimum required
> priv spec version is not satisfied. This also ensures that machines with
> priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
> extensions.
>
> Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
> device tree")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f3b61dfd63..25a4ba3e22 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -541,6 +541,40 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> set_priv_version(env, priv_version);
> }
>
> + /* Force disable extensions if priv spec version does not match */
> + if (env->priv_ver < PRIV_VERSION_1_12_0) {
> + cpu->cfg.ext_h = false;
> + cpu->cfg.ext_v = false;
> + cpu->cfg.ext_zfh = false;
> + cpu->cfg.ext_zfhmin = false;
> + cpu->cfg.ext_zfinx = false;
> + cpu->cfg.ext_zhinx = false;
> + cpu->cfg.ext_zhinxmin = false;
> + cpu->cfg.ext_zdinx = false;
> + cpu->cfg.ext_zba = false;
> + cpu->cfg.ext_zbb = false;
> + cpu->cfg.ext_zbc = false;
> + cpu->cfg.ext_zbkb = false;
> + cpu->cfg.ext_zbkc = false;
> + cpu->cfg.ext_zbkx = false;
> + cpu->cfg.ext_zbs = false;
> + cpu->cfg.ext_zk = false;
> + cpu->cfg.ext_zkn = false;
> + cpu->cfg.ext_zknd = false;
> + cpu->cfg.ext_zkne = false;
> + cpu->cfg.ext_zknh = false;
> + cpu->cfg.ext_zkr = false;
> + cpu->cfg.ext_zks = false;
> + cpu->cfg.ext_zksed = false;
> + cpu->cfg.ext_zksh = false;
> + cpu->cfg.ext_zkt = false;
> + cpu->cfg.ext_zve32f = false;
> + cpu->cfg.ext_zve64f = false;
> + cpu->cfg.ext_svinval = false;
> + cpu->cfg.ext_svnapot = false;
> + cpu->cfg.ext_svpbmt = false;
> + }
> +
This will not scale in future with new extensions in the next few
years. We probably need to make more intrusive changes to tie up the
min_version for extensions as well.
A brief look at the "Property" data structure and couldn't find an
easy way to do it.
For this patch,
Reviewed-by: Atish Patra <atishp@rivosinc.com>
> if (cpu->cfg.mmu) {
> riscv_set_feature(env, RISCV_FEATURE_MMU);
> }
> --
> 2.34.1
>
--
Regards,
Atish
- Re: [PATCH v2 2/8] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, (continued)
- [PATCH v2 3/8] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Anup Patel, 2022/05/11
- [PATCH v2 4/8] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Anup Patel, 2022/05/11
- [PATCH v2 5/8] target/riscv: Don't force update priv spec version to latest, Anup Patel, 2022/05/11
- [PATCH v2 6/8] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher, Anup Patel, 2022/05/11
- [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match, Anup Patel, 2022/05/11
[PATCH v2 8/8] hw/riscv: virt: Fix interrupt parent for dynamic platform devices, Anup Patel, 2022/05/11
Re: [PATCH v2 0/8] QEMU RISC-V nested virtualization fixes, Alistair Francis, 2022/05/24