Re: Modelling core local interrupts

[Frank Chang]

On Fri, Apr 22, 2022 at 8:41 AM vysakh pillai <vysakhpillai@gmail.com> wrote:

Hi,

I am looking for some reference code that will let me hook up a peripheral to the core local interrupt controller. I want to avoid going through the PLIC for modeling some simpler peripherals that directly interrupt the CPU. 

The polar fire SoC datasheet says " 48 interrupts from peripherals are directly connected as Local interrupts to each processor core". But the mpsoc machine model seems to be configuring everything via the PLIC. I also could not find peripherals being connected to the CLIC in any other machine model. 

Is the CLIC currently not modelled in RISC-V QEMU? OR, does the PLIC model behave similarly to CLIC in the current model?

Vysakh P Pillai

http://embeddedinn.xyz

For CLIC, there was a RFC patchet modeling RISC-V CLIC v0.9:

https://patchew.org/QEMU/20210409074857.166082-1-zhiwei_liu@c-sky.com/

I'm not sure whether the author has any plan to upstream the newer version of the patchset.

Regards,

Frank Chang