Re: [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin

[Richard Henderson]

On 12/30/21 7:23 PM, Weiwei Li wrote:
> From: liweiwei<liweiwei@iscas.ac.cn>
>
>    - update extension check REQUIRE_ZHINX_OR_ZFH and 
> REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
>    - update half float point register read/write
>    - disable nanbox_h check
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/fpu_helper.c                 |  89 +++---
>   target/riscv/helper.h                     |   2 +-
>   target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++-------
>   target/riscv/internals.h                  |  16 +-
>   4 files changed, 296 insertions(+), 143 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~