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[PATCH v2 0/3] support subsets of virtual memory extension
From: |
Weiwei Li |
Subject: |
[PATCH v2 0/3] support subsets of virtual memory extension |
Date: |
Fri, 31 Dec 2021 16:09:20 +0800 |
This patchset implements virtual memory related RISC-V extensions: Svnapot
version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
Specification:
https://github.com/riscv/virtual-memory/tree/main/specs
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v2
To test this implementation, specify cpu argument with
'x-svinval=true,x-svnapot=true,x-svpbmt=true'.
This implementation can pass the riscv-tests for rv64ssvnapot.
v2:
* add extension check for svnapot and svpbmt
Weiwei Li (3):
target/riscv: add support for svnapot extension
target/riscv: add support for svinval extension
target/riscv: add support for svpbmt extension
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 4 ++
target/riscv/cpu_helper.c | 27 ++++++--
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
7 files changed, 116 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
--
2.17.1
- [PATCH v2 0/3] support subsets of virtual memory extension,
Weiwei Li <=