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[PATCH 4/6] target/riscv: add support for zdinx
|
From: |
liweiwei |
|
Subject: |
[PATCH 4/6] target/riscv: add support for zdinx |
|
Date: |
Fri, 24 Dec 2021 11:49:13 +0800 |
-- update extension check REQUIRE_ZDINX_OR_D
-- update double float point register read/write
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvd.c.inc | 252 ++++++++++++++++--------
1 file changed, 174 insertions(+), 78 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 64fb0046f7..084a5c5fbe 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -18,6 +18,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_ZDINX_OR_D(ctx) do {\
+ if (!ctx->ext_zdinx) {\
+ REQUIRE_EXT(ctx, RVD); \
+ } \
+} while (0)
+
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
TCGv addr;
@@ -62,10 +68,16 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
+
gen_set_rm(ctx, a->rm);
- gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ gen_helper_fmadd_d(dest, cpu_env, src1, src2, src3);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -73,10 +85,16 @@ static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
+
gen_set_rm(ctx, a->rm);
- gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ gen_helper_fmsub_d(dest, cpu_env, src1, src2, src3);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -84,10 +102,16 @@ static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d
*a)
static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
+
gen_set_rm(ctx, a->rm);
- gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ gen_helper_fnmsub_d(dest, cpu_env, src1, src2, src3);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -95,10 +119,16 @@ static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d
*a)
static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ TCGv_i64 src3 = get_fpr_d(ctx, a->rs3);
+
gen_set_rm(ctx, a->rm);
- gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
- cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ gen_helper_fnmadd_d(dest, cpu_env, src1, src2, src3);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -106,12 +136,15 @@ static bool trans_fnmadd_d(DisasContext *ctx,
arg_fnmadd_d *a)
static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_d(dest, cpu_env, src1, src2);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -119,12 +152,15 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a)
static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_d(dest, cpu_env, src1, src2);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -132,12 +168,15 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a)
static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_d(dest, cpu_env, src1, src2);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -145,12 +184,15 @@ static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a)
static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_d(dest, cpu_env, src1, src2);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -158,23 +200,34 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a)
static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_d(dest, cpu_env, src1);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a)
{
+ REQUIRE_FPU;
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+
if (a->rs1 == a->rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ tcg_gen_mov_i64(dest, src1);
} else {
- tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2],
- cpu_fpr[a->rs1], 0, 63);
+ tcg_gen_deposit_i64(dest, src2,
+ src1, 0, 63);
}
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -182,15 +235,21 @@ static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d
*a)
static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+
if (a->rs1 == a->rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN);
+ tcg_gen_xori_i64(dest, src1, INT64_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
- tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63);
+ tcg_gen_not_i64(t0, src2);
+ tcg_gen_deposit_i64(dest, t0, src1, 0, 63);
tcg_temp_free_i64(t0);
}
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -198,15 +257,21 @@ static bool trans_fsgnjn_d(DisasContext *ctx,
arg_fsgnjn_d *a)
static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+
if (a->rs1 == a->rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN);
+ tcg_gen_andi_i64(dest, src1, ~INT64_MIN);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN);
- tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
+ tcg_gen_andi_i64(t0, src2, INT64_MIN);
+ tcg_gen_xor_i64(dest, src1, t0);
tcg_temp_free_i64(t0);
}
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -214,11 +279,14 @@ static bool trans_fsgnjx_d(DisasContext *ctx,
arg_fsgnjx_d *a)
static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ gen_helper_fmin_d(dest, cpu_env, src1, src2);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -226,11 +294,14 @@ static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a)
static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env,
- cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
+ gen_helper_fmax_d(dest, cpu_env, src1, src2);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -238,11 +309,14 @@ static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a)
static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_d(dest, cpu_env, src1);
+ gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -250,11 +324,14 @@ static bool trans_fcvt_s_d(DisasContext *ctx,
arg_fcvt_s_d *a)
static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
- gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_s(dest, cpu_env, src1);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
}
@@ -262,11 +339,13 @@ static bool trans_fcvt_d_s(DisasContext *ctx,
arg_fcvt_d_s *a)
static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_helper_feq_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -274,11 +353,13 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_helper_flt_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -286,11 +367,13 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
+ TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
- gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_helper_fle_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -298,11 +381,12 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
- gen_helper_fclass_d(dest, cpu_fpr[a->rs1]);
+ gen_helper_fclass_d(dest, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -310,12 +394,13 @@ static bool trans_fclass_d(DisasContext *ctx,
arg_fclass_d *a)
static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_helper_fcvt_w_d(dest, cpu_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -323,12 +408,13 @@ static bool trans_fcvt_w_d(DisasContext *ctx,
arg_fcvt_w_d *a)
static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_helper_fcvt_wu_d(dest, cpu_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -336,12 +422,14 @@ static bool trans_fcvt_wu_d(DisasContext *ctx,
arg_fcvt_wu_d *a)
static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src);
+ gen_helper_fcvt_d_w(dest, cpu_env, src);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
@@ -350,12 +438,14 @@ static bool trans_fcvt_d_w(DisasContext *ctx,
arg_fcvt_d_w *a)
static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
{
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src);
+ gen_helper_fcvt_d_wu(dest, cpu_env, src);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
@@ -365,12 +455,13 @@ static bool trans_fcvt_l_d(DisasContext *ctx,
arg_fcvt_l_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_helper_fcvt_l_d(dest, cpu_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -379,12 +470,13 @@ static bool trans_fcvt_lu_d(DisasContext *ctx,
arg_fcvt_lu_d *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_helper_fcvt_lu_d(dest, cpu_env, src1);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -407,12 +499,14 @@ static bool trans_fcvt_d_l(DisasContext *ctx,
arg_fcvt_d_l *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src);
+ gen_helper_fcvt_d_l(dest, cpu_env, src);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
@@ -422,12 +516,14 @@ static bool trans_fcvt_d_lu(DisasContext *ctx,
arg_fcvt_d_lu *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVD);
+ REQUIRE_ZDINX_OR_D(ctx);
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src);
+ gen_helper_fcvt_d_lu(dest, cpu_env, src);
+ gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
--
2.17.1
- [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, (continued)
- [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/23
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, Richard Henderson, 2021/12/24
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/24
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, Richard Henderson, 2021/12/25
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/25
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/25
- Re: [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, Richard Henderson, 2021/12/25
[PATCH 3/6] target/riscv: add support for zfinx, liweiwei, 2021/12/23
[PATCH 4/6] target/riscv: add support for zdinx,
liweiwei <=