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[PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
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From: |
liweiwei |
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Subject: |
[PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties |
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Date: |
Fri, 24 Dec 2021 11:49:15 +0800 |
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a5fa14f2ac..dbd15693be 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -657,6 +657,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
--
2.17.1
- [PATCH 0/6] support subsets of Float-Point in Integer Registers extensions, liweiwei, 2021/12/23
- [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}, liweiwei, 2021/12/23
- [PATCH 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties,
liweiwei <=
- [PATCH 5/6] target/riscv: add support for zhinx/zhinxmin, liweiwei, 2021/12/23
- [PATCH 2/6] target/riscv: add support for unique fpr read/write with support for zfinx, liweiwei, 2021/12/23