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[PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask loa
From: |
frank . chang |
Subject: |
[PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns |
Date: |
Fri, 10 Dec 2021 15:57:00 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.c.inc | 40 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 21 +++++++++++++
4 files changed, 67 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ab283d12b7..6e58343af3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -129,6 +129,8 @@ DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlm_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vsm_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3b6524bad9..1a4a287146 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -305,6 +305,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
+# Vector unit-stride mask load/store insns.
+vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
+vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
+
# Vector strided insns.
vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index e540b5d33c..97b1dc1026 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -697,6 +697,46 @@ GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op,
st_us_check)
GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check)
GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
+/*
+ *** unit stride mask load and store
+ */
+static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn = gen_helper_vlm_v;
+
+ /* EMUL = 1, NFIELDS = 1 */
+ data = FIELD_DP32(data, VDATA, LMUL, 0);
+ data = FIELD_DP32(data, VDATA, NF, 1);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
+}
+
+static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew)
+{
+ /* EMUL = 1, NFIELDS = 1 */
+ return require_rvv(s) && vext_check_isa_ill(s);
+}
+
+static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn = gen_helper_vsm_v;
+
+ /* EMUL = 1, NFIELDS = 1 */
+ data = FIELD_DP32(data, VDATA, LMUL, 0);
+ data = FIELD_DP32(data, VDATA, NF, 1);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
+}
+
+static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew)
+{
+ /* EMUL = 1, NFIELDS = 1 */
+ return require_rvv(s) && vext_check_isa_ill(s);
+}
+
+GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check)
+GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check)
+
/*
*** stride load and store
*/
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 83373ca6fc..4c1a1310e6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -345,6 +345,27 @@ GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
+/*
+ *** unit stride mask load and store, EEW = 1
+ */
+void HELPER(vlm_v)(void *vd, void *v0, target_ulong base,
+ CPURISCVState *env, uint32_t desc)
+{
+ /* evl = ceil(vl/8) */
+ uint8_t evl = (env->vl + 7) >> 3;
+ vext_ldst_us(vd, base, env, desc, lde_b,
+ 0, evl, GETPC(), MMU_DATA_LOAD);
+}
+
+void HELPER(vsm_v)(void *vd, void *v0, target_ulong base,
+ CPURISCVState *env, uint32_t desc)
+{
+ /* evl = ceil(vl/8) */
+ uint8_t evl = (env->vl + 7) >> 3;
+ vext_ldst_us(vd, base, env, desc, ste_b,
+ 0, evl, GETPC(), MMU_DATA_STORE);
+}
+
/*
*** index: access vector element from indexed memory
*/
--
2.31.1
- [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, (continued)
- [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/12/10
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/12/10
- [PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/12/10
- [PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/12/10
- [PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/12/10
- [PATCH v11 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/12/10
- [PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/12/10
- [PATCH v11 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns,
frank . chang <=
- [PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/12/10
- [PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/12/10
- [PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/12/10
- [PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/12/10
- [PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/12/10
- [PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/12/10
- Re: [PATCH v11 00/77] support vector extension v1.0, Alistair Francis, 2021/12/16