[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point red
From: |
frank . chang |
Subject: |
[PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction |
Date: |
Fri, 10 Dec 2021 15:56:39 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++---
target/riscv/vector_helper.c | 12 ++++++------
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index f5588d9832..998247d71d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2637,9 +2637,15 @@ GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
-GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
-GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
-GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
+static bool freduction_check(DisasContext *s, arg_rmrr *a)
+{
+ return reduction_check(s, a) &&
+ require_rvf(s);
+}
+
+GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
+GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
+GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c95c8bd9db..79a2c3ff3a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4173,14 +4173,14 @@ GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4,
H4, float32_add)
GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2,
float16_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4,
float32_maximum_number)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8,
float64_maximum_number)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2,
float16_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4,
float32_minimum_number)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8,
float64_minimum_number)
/* Vector Widening Floating-Point Reduction Instructions */
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
--
2.31.1
- [PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, (continued)
- [PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/12/10
- [PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/12/10
- [PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/12/10
- [PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/12/10
- [PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/12/10
- [PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/12/10
- [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/12/10
- [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/12/10
- [PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/12/10
- [PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction,
frank . chang <=
- [PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/12/10
- [PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/12/10
- [PATCH v11 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/12/10
- [PATCH v11 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/12/10
- [PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/12/10
- [PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/12/10
- [PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/12/10
- [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/12/10
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/12/10