[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root inst
|
From: |
frank . chang |
|
Subject: |
[PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root instruction |
|
Date: |
Fri, 10 Dec 2021 15:56:13 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7d8441d1f2..92a0e6fe51 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -563,7 +563,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.31.1
- [PATCH v11 14/77] target/riscv: rvv-1.0: add VMA and VTA, (continued)
- [PATCH v11 14/77] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/12/10
- [PATCH v11 19/77] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/12/10
- [PATCH v11 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2021/12/10
- [PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/12/10
- [PATCH v11 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2021/12/10
- [PATCH v11 21/77] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/12/10
- [PATCH v11 24/77] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/12/10
- [PATCH v11 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/12/10
- [PATCH v11 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/12/10
- [PATCH v11 28/77] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/12/10
- [PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root instruction,
frank . chang <=
- [PATCH v11 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/12/10
- [PATCH v11 29/77] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/12/10
- [PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/12/10
- [PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/12/10
- [PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/12/10
- [PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/12/10
- [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/12/10
- [PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/12/10
- [PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/12/10