[PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

qemu-riscv

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[PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

From:	Anup Patel
Subject:	[PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs
Date:	Tue, 26 Oct 2021 12:12:07 +0530

A hypervsior can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c      |  3 ++-
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/csr.c      | 18 +++++++++++-------
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c..0460a3972b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
     }
     env->mcause = 0;
+    env->miclaim = MIP_SGEIP;
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
 #endif
@@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
     cpu_set_cpustate_pointers(cpu);
 
 #ifndef CONFIG_USER_ONLY
-    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
+    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
 #endif /* CONFIG_USER_ONLY */
 }
 
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index cffcd3a5df..8a5a4cde95 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -498,6 +498,8 @@ typedef enum RISCVException {
 #define IRQ_S_EXT                          9
 #define IRQ_VS_EXT                         10
 #define IRQ_M_EXT                          11
+#define IRQ_S_GEXT                         12
+#define IRQ_LOCAL_MAX                      13
 
 /* mip masks */
 #define MIP_USIP                           (1 << IRQ_U_SOFT)
@@ -512,6 +514,7 @@ typedef enum RISCVException {
 #define MIP_SEIP                           (1 << IRQ_S_EXT)
 #define MIP_VSEIP                          (1 << IRQ_VS_EXT)
 #define MIP_MEIP                           (1 << IRQ_M_EXT)
+#define MIP_SGEIP                          (1 << IRQ_S_GEXT)
 
 /* sip masks */
 #define SIP_SSIP                           MIP_SSIP
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9dfc9b5eba..9a0a0c0679 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -408,12 +408,13 @@ static RISCVException read_timeh(CPURISCVState *env, int 
csrno,
 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
+#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
 
 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
                                            VS_MODE_INTERRUPTS;
 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
-                                     VS_MODE_INTERRUPTS;
+                                     HS_MODE_INTERRUPTS;
 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
@@ -673,7 +674,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int 
csrno,
 {
     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
     if (riscv_has_ext(env, RVH)) {
-        env->mideleg |= VS_MODE_INTERRUPTS;
+        env->mideleg |= HS_MODE_INTERRUPTS;
     }
     return RISCV_EXCP_NONE;
 }
@@ -689,6 +690,9 @@ static RISCVException write_mie(CPURISCVState *env, int 
csrno,
                                 target_ulong val)
 {
     env->mie = (env->mie & ~all_ints) | (val & all_ints);
+    if (!riscv_has_ext(env, RVH)) {
+        env->mie &= ~MIP_SGEIP;
+    }
     return RISCV_EXCP_NONE;
 }
 
@@ -984,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
     }
 
     if (ret_value) {
-        *ret_value &= env->mideleg;
+        *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
     }
     return ret;
 }
@@ -1102,7 +1106,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int 
csrno,
                       write_mask & hvip_writable_mask);
 
     if (ret_value) {
-        *ret_value &= hvip_writable_mask;
+        *ret_value &= VS_MODE_INTERRUPTS;
     }
     return ret;
 }
@@ -1115,7 +1119,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int 
csrno,
                       write_mask & hip_writable_mask);
 
     if (ret_value) {
-        *ret_value &= hip_writable_mask;
+        *ret_value &= HS_MODE_INTERRUPTS;
     }
     return ret;
 }
@@ -1123,14 +1127,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int 
csrno,
 static RISCVException read_hie(CPURISCVState *env, int csrno,
                                target_ulong *val)
 {
-    *val = env->mie & VS_MODE_INTERRUPTS;
+    *val = env->mie & HS_MODE_INTERRUPTS;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException write_hie(CPURISCVState *env, int csrno,
                                 target_ulong val)
 {
-    target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & 
VS_MODE_INTERRUPTS);
+    target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & 
HS_MODE_INTERRUPTS);
     return write_mie(env, CSR_MIE, newval);
 }
 
-- 
2.25.1

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[PATCH v4 00/22] QEMU RISC-V AIA support, Anup Patel, 2021/10/26
- [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/10/26
- [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/10/26
- [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/10/26
- [PATCH v4 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/10/26
- [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/10/26
- [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/10/26
  - Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2021/10/31
- [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel <=
- [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/10/26
- [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/10/26
- [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/10/26
- [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/10/26
- [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/10/26
- [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/10/26
- [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/10/26
- [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/10/26
- [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/10/26
- [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2021/10/26

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