Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upp

qemu-riscv

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Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upp

From:	Richard Henderson
Subject:	Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part
Date:	Wed, 20 Oct 2021 08:09:13 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/19/21 2:47 AM, Frédéric Pétrot wrote:

+static TCGv get_gprh(DisasContext *ctx, int reg_num)
+{
+    if (reg_num == 0 || get_ol(ctx) < MXL_RV128) {
+        return ctx->zero;
+    }


So... why return anything for OL < 128?
Seems like that should be a bug.

+static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
+{
+    if (reg_num != 0) {
+        if (get_ol(ctx) < MXL_RV128) {
+            tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63);
+        } else {
+            tcg_gen_mov_tl(cpu_gprh[reg_num], t);
+        }
+    }

Hmm... this implies that you must set the low part first, which could be easy to mis-use.Probably better to create a combined gen_set_gpr128 that takes both halves at once.

+    /* devilish temporary code so that the patch compiles */
+    if (get_xl_max(ctx) == MXL_RV128) {
+        (void)get_gprh(ctx, 6);
+        (void)dest_gprh(ctx, 6);
+        gen_set_gprh(ctx, 6, NULL);
+    }

I don't think it would be confusing to squash this patch into the next one, which adds theactual uses.

r~

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[PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, (continued)
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Richard Henderson, 2021/10/20
    - Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/22
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Richard Henderson, 2021/10/20
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/20
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 01/21] memory: change define name for consistency, Philippe Mathieu-Daudé, 2021/10/20
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Richard Henderson <=
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/20
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Richard Henderson, 2021/10/20
- [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Richard Henderson, 2021/10/20
- [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/10/20
    - Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/20
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19

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