[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64
|
From: |
Richard Henderson |
|
Subject: |
[PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 |
|
Date: |
Mon, 18 Oct 2021 17:01:03 -0700 |
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+ tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+ return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
--
2.25.1
- [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, (continued)
- [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/18
- [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/18
- [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/18
- [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/18
- [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/18
- [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/18
- [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/18
- [PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/18
- [PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64,
Richard Henderson <=
- [PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/18
- [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/18
- [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/18
- [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump, Richard Henderson, 2021/10/18