Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasCont

qemu-riscv

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Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasCont

From:	Richard Henderson
Subject:	Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
Date:	Thu, 14 Oct 2021 08:39:32 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/14/21 1:57 AM, Frédéric Pétrot wrote:

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5724a62bb0..6ab5c6aa58 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,7 +67,7 @@ typedef struct DisasContext {
          to any system register, which includes CSR_FRM, so we do not have
          to reset this known value.  */
       int frm;
-    bool w;
+    RISCVMXL ol;


Why not directly use the xl?


   Hi Zhiwei,

   I am not speaking for Richard, but my understanding is that 'ol' is linked to
   the instruction being translated, suffixed by 'w' in rv64 and 'w' and 'd' in
   rv128, while 'xl' is the value in mstatus (or misa) depending on the register
   size of the current execution (mxl, sxl, uxl).


Correct.


r~

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[PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, (continued)
- [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/13
- [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/13
- [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, LIU Zhiwei, 2021/10/14
  - Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Alistair Francis, 2021/10/15
- [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Alistair Francis, 2021/10/15
- [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, LIU Zhiwei, 2021/10/14
    - Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Frédéric Pétrot, 2021/10/14
    - Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson <=
  - Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Alistair Francis, 2021/10/15
- [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/13
  - Re: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, LIU Zhiwei, 2021/10/14
  - Re: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, Alistair Francis, 2021/10/15
- [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/13

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