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[PATCH v2 13/27] target/riscv: rename a few gen function helpers
From: |
Frédéric Pétrot |
Subject: |
[PATCH v2 13/27] target/riscv: rename a few gen function helpers |
Date: |
Wed, 6 Oct 2021 23:28:19 +0200 |
Add the tl suffix to the existing integer gen_xxx functions that apply to
target_long types for which a 128-bit version will also exist, so
that it is immediately visible which function is for which type(s).
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++++++---------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 9e5782d1f5..ab85693364 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -136,7 +136,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -152,6 +152,11 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp
memop)
return true;
}
+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+ return gen_load_tl(ctx, a, memop);
+}
+
static bool trans_lb(DisasContext *ctx, arg_lb *a)
{
return gen_load(ctx, a, MO_SB);
@@ -189,7 +194,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
return gen_load(ctx, a, MO_TEQ);
}
-static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
@@ -204,6 +209,11 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp
memop)
return true;
}
+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+ return gen_store_tl(ctx, a, memop);
+}
+
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
@@ -231,12 +241,12 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
}
-static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
+static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
}
-static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+static void gen_sltu_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
@@ -244,13 +254,13 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_slt, gen_slt, NULL);
+ gen_slt_lt, gen_slt_lt, NULL);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_sltu, gen_sltu, NULL);
+ gen_sltu_lt, gen_sltu_lt, NULL);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -306,12 +316,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN, gen_slt_lt, gen_slt_lt, NULL);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
+ return gen_arith(ctx, a, EXT_SIGN, gen_sltu_lt, gen_sltu_lt, NULL);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -353,7 +363,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
}
-static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
@@ -362,10 +372,10 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw_tl, NULL);
}
-static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
@@ -374,7 +384,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw_tl, NULL);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
--
2.33.0
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, (continued)
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/06
- [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/06
- [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith, Frédéric Pétrot, 2021/10/06
- [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/06
- [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 12/27] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 16/27] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/06
- [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 13/27] target/riscv: rename a few gen function helpers,
Frédéric Pétrot <=
- [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic, Frédéric Pétrot, 2021/10/06
- [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit, Frédéric Pétrot, 2021/10/06
- [PATCH v2 22/27] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/06
- [PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/06
- [PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs, Frédéric Pétrot, 2021/10/06