[PATCH 0/1] Proposing custom CSR handling logic

[Ruinland Chuan-Tzu Tsai]

Hi all,

It seesm that Nuclei System Technology has sent out their platform 
support patches and there are concern regarding introducing intrusive
non-standard code into QEMU base. Since we have been discussed with
Nuclei couples of months ago, and thus we decide it's time for us to
join the party.

As we discussed with Nuclei privately, we basically borrows the idea
from Renode's own QEMU/TCG fork - - introducing extralogic on
riscv_csrrw().

Just for the show start, we have been ported our custom instruction
handling code and testing internally quite a while. Currently we can
boot Linux with OpenSBI succcesfully, and we will upstrean the code
as soon as possible.

Cordially yours,
Ruinland

Ruinland Chuan-Tzu Tsai (1):
  Adding premliminary support for custom CSR handling mechanism

 target/riscv/cpu.c      |  28 ++++++++++
 target/riscv/cpu.h      |  12 ++++-
 target/riscv/cpu_bits.h | 115 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/csr.c      | 107 +++++++++++++++++++++++++++++++++++--
 4 files changed, 256 insertions(+), 6 deletions(-)

-- 
2.17.1