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[PATCH v3 10/10] target/riscv: Fix the RV64H decode comment
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From: |
Alistair Francis |
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Subject: |
[PATCH v3 10/10] target/riscv: Fix the RV64H decode comment |
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Date: |
Sat, 24 Apr 2021 13:34:37 +1000 |
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fecf0f15d5..8901ba1e1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32H Base Instruction Set ***
+# *** RV64H Base Instruction Set ***
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
--
2.31.1
- [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro, (continued)
- [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/04/23
- [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/04/23
- [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/04/23
- [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/04/23
- [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/04/23
[PATCH v3 09/10] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/04/23
[PATCH v3 10/10] target/riscv: Fix the RV64H decode comment,
Alistair Francis <=
Re: [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on, Alistair Francis, 2021/04/25