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Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR ope
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations |
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Date: |
Tue, 6 Apr 2021 16:34:39 +0800 |
On Thu, Apr 1, 2021 at 11:20 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 14 +-
> target/riscv/csr.c | 643 +++++++++++++++++++++++++++------------------
> 2 files changed, 390 insertions(+), 267 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions, (continued)
- [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/04/01
- [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/04/01
- [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/04/01
- [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/04/01
- [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/04/01
- Re: [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use, Alistair Francis, 2021/04/07