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[PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing
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From: |
frank . chang |
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Subject: |
[PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs |
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Date: |
Fri, 26 Feb 2021 11:18:51 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aa76da9e185..e0f1106d909 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -293,7 +293,7 @@ static int write_vxrm(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxrm = val;
@@ -312,7 +312,7 @@ static int write_vxsat(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxsat = val;
@@ -331,7 +331,7 @@ static int write_vstart(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
/*
@@ -354,7 +354,7 @@ static int write_vcsr(CPURISCVState *env, int csrno,
target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
--
2.17.1
- [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction, (continued)
- [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/02/25
- [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/02/25
- [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/02/25
- [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/02/25
- [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/02/25
- [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/02/25
- [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/02/25
- [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/02/25
- [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/02/25
- [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs,
frank . chang <=
- [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/02/25
- [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/02/25
- [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/02/25
- [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/02/25
- [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/02/25
- [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/02/25
- [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/02/25