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[PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions |
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Date: |
Fri, 12 Feb 2021 23:02:52 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 4 ++++
target/riscv/insn32-64.decode | 4 ++++
target/riscv/insn_trans/trans_rvp.c.inc | 5 ++++
target/riscv/packed_helper.c | 31 +++++++++++++++++++++++++
4 files changed, 44 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 198b010601..05f7c1d811 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1453,4 +1453,8 @@ DEF_HELPER_4(kdmatt16, tl, env, tl, tl, tl)
DEF_HELPER_3(smbt32, tl, env, tl, tl)
DEF_HELPER_3(smtt32, tl, env, tl, tl)
+
+DEF_HELPER_4(kmabb32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmabt32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmatt32, tl, env, tl, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 46a4e5d080..c5b07a2667 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -148,3 +148,7 @@ kdmatt16 1111100 ..... ..... 001 ..... 1111111 @r
smbt32 0001100 ..... ..... 010 ..... 1111111 @r
smtt32 0010100 ..... ..... 010 ..... 1111111 @r
+
+kmabb32 0101101 ..... ..... 010 ..... 1111111 @r
+kmabt32 0110101 ..... ..... 010 ..... 1111111 @r
+kmatt32 0111101 ..... ..... 010 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 33435c3a9e..da6a4ba14a 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1194,4 +1194,9 @@ GEN_RVP_R_ACC_OOL(kdmatt16);
/* (RV64 Only) 32-bit Multiply Instructions */
GEN_RVP_R_OOL(smbt32);
GEN_RVP_R_OOL(smtt32);
+
+/* (RV64 Only) 32-bit Multiply & Add Instructions */
+GEN_RVP_R_ACC_OOL(kmabb32);
+GEN_RVP_R_ACC_OOL(kmabt32);
+GEN_RVP_R_ACC_OOL(kmatt32);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 11b41637a1..99da28a4b3 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3592,4 +3592,35 @@ static inline void do_smtt32(CPURISCVState *env, void
*vd, void *va,
}
RVPR(smtt32, 1, sizeof(target_ulong));
+
+/* (RV64 Only) 32-bit Multiply & Add Instructions */
+static inline void do_kmabb32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ *d = sadd64(env, 0, (int64_t)a[H4(2 * i)] * b[H4(2 * i)], *c);
+}
+
+RVPR_ACC(kmabb32, 1, sizeof(target_ulong));
+
+static inline void do_kmabt32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ *d = sadd64(env, 0, (int64_t)a[H4(2 * i)] * b[H4(2 * i + 1)], *c);
+}
+
+RVPR_ACC(kmabt32, 1, sizeof(target_ulong));
+
+static inline void do_kmatt32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ *d = sadd64(env, 0, (int64_t)a[H4(2 * i + 1)] * b[H4(2 * i + 1)], *c);
+}
+
+RVPR_ACC(kmatt32, 1, sizeof(target_ulong));
#endif
--
2.17.1
- [PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions, (continued)
- [PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 27/38] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions,
LIU Zhiwei <=
- [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 38/38] target/riscv: configure and turn on packed extension from command line, LIU Zhiwei, 2021/02/12