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[PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions |
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Date: |
Fri, 12 Feb 2021 23:02:39 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvp.c.inc | 5 +++
target/riscv/packed_helper.c | 44 +++++++++++++++++++++++++
4 files changed, 57 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7c3a0654d6..0ddd07b305 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1323,3 +1323,7 @@ DEF_HELPER_2(clz32, tl, env, tl)
DEF_HELPER_2(clo32, tl, env, tl)
DEF_HELPER_3(pbsad, tl, env, tl, tl)
DEF_HELPER_4(pbsada, tl, env, tl, tl, tl)
+
+DEF_HELPER_4(smaqa, tl, env, tl, tl, tl)
+DEF_HELPER_4(umaqa, tl, env, tl, tl, tl)
+DEF_HELPER_4(smaqa_su, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 12e95f9c5f..6a50abca21 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -793,3 +793,7 @@ clz32 1010111 11001 ..... 000 ..... 1111111 @r2
clo32 1010111 11011 ..... 000 ..... 1111111 @r2
pbsad 1111110 ..... ..... 000 ..... 1111111 @r
pbsada 1111111 ..... ..... 000 ..... 1111111 @r
+
+smaqa 1100100 ..... ..... 000 ..... 1111111 @r
+umaqa 1100110 ..... ..... 000 ..... 1111111 @r
+smaqa_su 1100101 ..... ..... 000 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 42656682c6..0877cd04b4 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -665,3 +665,8 @@ GEN_RVP_R2_OOL(clz32);
GEN_RVP_R2_OOL(clo32);
GEN_RVP_R_OOL(pbsad);
GEN_RVP_R_ACC_OOL(pbsada);
+
+/* 8-bit Multiply with 32-bit Add Instructions */
+GEN_RVP_R_ACC_OOL(smaqa);
+GEN_RVP_R_ACC_OOL(umaqa);
+GEN_RVP_R_ACC_OOL(smaqa_su);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 96e73c045b..02a0f912e9 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -2053,3 +2053,47 @@ static inline void do_pbsada(CPURISCVState *env, void
*vd, void *va,
}
RVPR_ACC(pbsada, 1, 1);
+
+/* 8-bit Multiply with 32-bit Add Instructions */
+static inline void do_smaqa(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int8_t *a = va, *b = vb;
+ int32_t *d = vd, *c = vc;
+
+ d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] +
+ a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] +
+ a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] +
+ a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)];
+}
+
+RVPR_ACC(smaqa, 1, 4);
+
+static inline void do_umaqa(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ uint8_t *a = va, *b = vb;
+ uint32_t *d = vd, *c = vc;
+
+ d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] +
+ a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] +
+ a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] +
+ a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)];
+}
+
+RVPR_ACC(umaqa, 1, 4);
+
+static inline void do_smaqa_su(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int8_t *a = va;
+ uint8_t *b = vb;
+ int32_t *d = vd, *c = vc;
+
+ d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] +
+ a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] +
+ a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] +
+ a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)];
+}
+
+RVPR_ACC(smaqa_su, 1, 4);
--
2.17.1
- [PATCH 01/38] target/riscv: implementation-defined constant parameters, (continued)
- [PATCH 01/38] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2021/02/12
- [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 15/38] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions,
LIU Zhiwei <=
- [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 27/38] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12