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Re: [PATCH v2 3/4] Add ePMP CSR accesses
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 3/4] Add ePMP CSR accesses |
Date: |
Wed, 10 Feb 2021 12:11:32 -0800 |
On Mon, Aug 10, 2020 at 5:24 PM Hou Weiying <weiying_hou@outlook.com> wrote:
>
> Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
> Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
> ---
> target/riscv/csr.c | 18 ++++++++++++++++++
> target/riscv/pmp.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6a96a01b1c..0bb33baec3 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -104,6 +104,11 @@ static int hmode(CPURISCVState *env, int csrno)
> return -1;
> }
>
> +static int epmp(CPURISCVState *env, int csrno)
> +{
> + return -!(env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP));
RISCV_FEATURE_EPMP isn't defined yet, so this fails to compile.
Alistair
> +}
> +
> static int pmp(CPURISCVState *env, int csrno)
> {
> return -!riscv_feature(env, RISCV_FEATURE_PMP);
> @@ -1142,6 +1147,18 @@ static int write_pmpaddr(CPURISCVState *env, int
> csrno, target_ulong val)
> return 0;
> }
>
> +static int read_mseccfg(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = mseccfg_csr_read(env);
> + return 0;
> +}
> +
> +static int write_mseccfg(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + mseccfg_csr_write(env, val);
> + return 0;
> +}
> +
> #endif
>
> /*
> @@ -1353,6 +1370,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTINST] = { hmode, read_mtinst, write_mtinst
> },
>
> /* Physical Memory Protection */
> + [CSR_MSECCFG] = { epmp, read_mseccfg, write_mseccfg
> },
> [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg
> },
> [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr
> },
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index b1fa703aff..97aab0b99e 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -494,3 +494,43 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env,
> uint32_t addr_index)
>
> return val;
> }
> +
> +
> +/*
> + * Handle a write to a mseccfg CSR
> + */
> +void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> +{
> + int i;
> +
> + if (!MSECCFG_RLB_ISSET(env)) {
> + for (i = 0; i < MAX_RISCV_PMPS; i++) {
> + if (pmp_is_locked(env, i)) {
> + /*
> + * Now that mseccfg.rlb is zero
> + * the value of mseccfg.rlb should be locked.
> + */
> + val &= ~MSECCFG_RLB;
> + break;
> + }
> + }
> + }
> +
> + /*
> + * sticky bit
> + */
> + val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> +
> + env->mseccfg = val;
> + trace_mseccfg_csr_write(env->mhartid, val);
> +}
> +
> +
> +/*
> + * Handle a read from a mseccfg CSR
> + */
> +target_ulong mseccfg_csr_read(CPURISCVState *env)
> +{
> + trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
> + return env->mseccfg;
> +}
> --
> 2.20.1
>
>
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