Re: [PATCH v6 0/6] RISC-V Pointer Masking implementation

[Richard Henderson]

On 10/23/20 5:25 PM, Alistair Francis wrote:
> On Thu, Oct 22, 2020 at 1:04 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>>
>> Hi,
>>
>> Added missing sign-off on the first patch.
>>
>> Thanks
>>
>> Alexey Baturo (5):
>>   [RISCV_PM] Add J-extension into RISC-V
>>   [RISCV_PM] Support CSRs required for RISC-V PM extension except for
>>     ones in hypervisor mode
>>   [RISCV_PM] Print new PM CSRs in QEMU logs
>>   [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
>>     instructions
>>   [RISCV_PM] Allow experimental J-ext to be turned on
>>
>> Anatoly Parshintsev (1):
>>   [RISCV_PM] Implement address masking functions required for RISC-V
>>     Pointer Masking extension
> 
> Thanks for the patches!
> 
> I don't know a lot about the J-extension, so it will take me some time
> to read into it before I can review this.
> 
> Maybe you can convince Richard to review it for you :P

Richard did review v3.  Alexey seems to have misplaced or not added the r-b
tags.  Although I missed that it misses the mask for the special hypervisor
load/store insns?


r~