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Re: [PATCH v5 0/6] RISC-V Pointer Masking implementation


From: no-reply
Subject: Re: [PATCH v5 0/6] RISC-V Pointer Masking implementation
Date: Thu, 22 Oct 2020 00:57:43 -0700 (PDT)

Patchew URL: 
20201022074309.3210-1-space.monkey.delivers@gmail.com/">https://patchew.org/QEMU/20201022074309.3210-1-space.monkey.delivers@gmail.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20201022074309.3210-1-space.monkey.delivers@gmail.com
Subject: [PATCH v5 0/6] RISC-V Pointer Masking implementation

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20201021163136.27324-1-alex.bennee@linaro.org -> 
patchew/20201021163136.27324-1-alex.bennee@linaro.org
 - [tag update]      patchew/20201021212721.440373-1-peterx@redhat.com -> 
patchew/20201021212721.440373-1-peterx@redhat.com
 * [new tag]         
patchew/20201022074309.3210-1-space.monkey.delivers@gmail.com -> 
patchew/20201022074309.3210-1-space.monkey.delivers@gmail.com
Switched to a new branch 'test'
047d80b Allow experimental J-ext to be turned on
2f7a895 Implement address masking functions required for RISC-V Pointer Masking 
extension
68d35c2 Support pointer masking for RISC-V for i/c/f/d/a types of instructions
19b617f Print new PM CSRs in QEMU logs
97bfef1 Support CSRs required for RISC-V PM extension except for ones in 
hypervisor mode
a02813c Add J-extension into RISC-V

=== OUTPUT BEGIN ===
1/6 Checking commit a02813c05dac (Add J-extension into RISC-V)
ERROR: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 21 lines checked

Patch 1/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/6 Checking commit 97bfef184299 (Support CSRs required for RISC-V PM extension 
except for ones in hypervisor mode)
3/6 Checking commit 19b617fc2d40 (Print new PM CSRs in QEMU logs)
4/6 Checking commit 68d35c24e0d4 (Support pointer masking for RISC-V for 
i/c/f/d/a types of instructions)
5/6 Checking commit 2f7a895949b8 (Implement address masking functions required 
for RISC-V Pointer Masking extension)
6/6 Checking commit 047d80ba64a4 (Allow experimental J-ext to be turned on)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20201022074309.3210-1-space.monkey.delivers@gmail.com/testing.checkpatch/?type=message">http://patchew.org/logs/20201022074309.3210-1-space.monkey.delivers@gmail.com/testing.checkpatch/?type=message.
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