RE: [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address

[Jiangyifei]

> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Thursday, October 15, 2020 4:22 AM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: palmer@dabbelt.com; Alistair.Francis@wdc.com;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Wubin (H) <wu.wubin@huawei.com>;
> Zhanghailiang <zhang.zhanghailiang@huawei.com>; dengkai (A)
> <dengkai1@huawei.com>; yinyipeng <yinyipeng1@huawei.com>
> Subject: Re: [PATCH V3] target/riscv: raise exception to HS-mode at
> get_physical_address
> 
> On 10/14/20 3:17 AM, Yifei Jiang wrote:
> > +                if (fault_pte_addr) {
> > +                    *fault_pte_addr = (base + idx * ptesize) >> 2;
> 
> The shift is wrong.  It should be exactly like...
> 

We have tested in the VM migration.

fault_pte_addr will eventually be assigned to htval register.

Description of htval register according to the specification:
When a guest-page-fault trap is taken into HS-mode, htval is written with 
either zero
or the guest physical address that faulted, shifted right by 2 bits.

In addition, fault_pte_addr is named after env->guest_phys_fault_addr, which 
makes
sense in a sense.

Yifei

> > +                }
> > +                return TRANSLATE_G_STAGE_FAIL;
> >              }
> >
> >              pte_addr = vbase + idx * ptesize;
> 
> ... this.
> 
> 
> r~