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Re: [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64 |
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Date: |
Sat, 29 Aug 2020 18:57:18 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +++ b/gdb-xml/riscv-64bit-csr.xml
> @@ -248,4 +248,11 @@
> <reg name="mucounteren" bitsize="64"/>
> <reg name="mscounteren" bitsize="64"/>
> <reg name="mhcounteren" bitsize="64"/>
> + <reg name="vstart" bitsize="64" group="vector"/>
> + <reg name="vxsat" bitsize="64" group="vector"/>
> + <reg name="vxrm" bitsize="64" group="vector"/>
> + <reg name="vcsr" bitsize="64" group="vector"/>
> + <reg name="vl" bitsize="64" group="vector"/>
> + <reg name="vtype" bitsize="64" group="vector"/>
> + <reg name="vlenb" bitsize="64" group="vector"/>
Just because these are csr's doesn't mean they're unrelated to RVV. I would
think that ideally they would be in the (generated) RVV-related xml file.
But I'm certainly not a gdb expert. So if that doesn't work, fine, leave it as
is.
However, if you leave these in the csr section, I think the next patch has to
be folded in, because you've already included
> #if defined(TARGET_RISCV32)
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> - 241, "riscv-32bit-csr.xml", 0);
> + 248, "riscv-32bit-csr.xml", 0);
... this.
That said, the actual dynamic xml looks fine.
r~
- Re: [RFC v4 64/70] target/riscv: rvv-1.0: widening floating-point/integer type-convert, (continued)
- [RFC v4 65/70] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/08/17
- [RFC v4 66/70] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/08/17
- [RFC v4 67/70] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 512-bits, frank . chang, 2020/08/17
- [RFC v4 68/70] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/08/17
- [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/08/17
- Re: [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64,
Richard Henderson <=
- [RFC v4 70/70] target/riscv: gdb: support vector registers for rv32, frank . chang, 2020/08/17
- Re: [RFC v4 00/70] support vector extension v1.0, Frank Chang, 2020/08/25