Re: [RFC v4 22/70] target/riscv: rvv-1.0: amo operations

[Richard Henderson]

On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> +static bool vext_check_amo(DisasContext *s, int vd, int vs2,
> +                           int wd, int vm, uint8_t eew)
> +{
> +    int8_t emul = ctzl(eew) - (s->sew + 3) + s->lmul;
> +    bool ret = has_ext(s, RVA) &&
> +               (1 << s->sew >= 4) &&
> +               (1 << s->sew <= sizeof(target_ulong)) &&
> +               (eew <= (sizeof(target_ulong) << 3))  &&
> +               require_align(vd, 1 << s->lmul) &&
> +               require_align(vs2, 1 << emul) &&
> +               (emul >= -3 && emul <= 3);
> +    if (wd) {
> +        ret &= require_vm(vm, vd);
> +        if (eew > (1 << (s->sew + 3))) {
> +            if (vd != vs2) {
> +                ret &= require_noover(vd, 1 << s->lmul, vs2, 1 << emul);
> +            }
> +        } else if (eew < (1 << (s->sew + 3))) {
> +            if (emul < 0) {
> +                ret &= require_noover(vd, 1 << s->lmul, vs2, 1 << emul);
> +            } else {
> +                ret &= require_noover_widen(vd, 1 << s->lmul, vs2, 1 << 
> emul);
> +            }
> +        }
> +    }
> +    return ret;
> +}

Same comments for EEW and require_noover.

r~