[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_i
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() |
|
Date: |
Wed, 12 Aug 2020 16:16:08 -0700 |
On Wed, Jul 29, 2020 at 4:32 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> When RISCV_FEATURE_TINST feature is enabled, we should write
> transformed instruction encoding of the trapped instruction
> in MTINST/HTINST CSR at time of taking trap.
>
> We update riscv_cpu_do_interrupt() as-per above.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu_helper.c | 166 +++++++++++++++++++++++++++++++++++++-
> target/riscv/instmap.h | 41 ++++++++++
> 2 files changed, 204 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e4bd45d66a..97ae23ad2b 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -22,6 +22,7 @@
> #include "qemu/main-loop.h"
> #include "cpu.h"
> #include "exec/exec-all.h"
> +#include "instmap.h"
> #include "tcg/tcg-op.h"
> #include "trace.h"
>
> @@ -820,6 +821,151 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> #endif
> }
>
> +static target_ulong riscv_transformed_insn(CPURISCVState *env,
> + int xlen, target_ulong insn)
> +{
> + target_ulong xinsn = 0;
> +
> + if ((insn & 0x3) != 0x3) {
> + /* Transform 16bit instruction into 32bit instruction */
> + switch (GET_C_OP(insn)) {
> + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */
> + switch (GET_C_FUNC(insn)) {
> + case OPC_RISC_C_FUNC_FLD_LQ:
> + if (xlen != 128) { /* C.FLD (RV32/64) */
> + xinsn = OPC_RISC_FLD;
> + xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn));
> + }
> + break;
> + case OPC_RISC_C_FUNC_LW: /* C.LW */
> + xinsn = OPC_RISC_LW;
> + xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn));
> + break;
> + case OPC_RISC_C_FUNC_FLW_LD:
> + if (xlen == 32) { /* C.FLW (RV32) */
> + xinsn = OPC_RISC_FLW;
> + xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn));
> + } else { /* C.LD (RV64/RV128) */
> + xinsn = OPC_RISC_LD;
> + xinsn = SET_RD(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn));
> + }
> + break;
> + case OPC_RISC_C_FUNC_FSD_SQ:
> + if (xlen != 128) { /* C.FSD (RV32/64) */
> + xinsn = OPC_RISC_FSD;
> + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn));
> + }
> + break;
> + case OPC_RISC_C_FUNC_SW: /* C.SW */
> + xinsn = OPC_RISC_SW;
> + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn));
> + break;
> + case OPC_RISC_C_FUNC_FSW_SD:
> + if (xlen == 32) { /* C.FSW (RV32) */
> + xinsn = OPC_RISC_FSW;
> + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn));
> + } else { /* C.SD (RV64/RV128) */
> + xinsn = OPC_RISC_SD;
> + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn));
> + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn));
> + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn));
> + }
> + break;
> + default:
> + break;
> + }
> + break;
> + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */
> + switch (GET_C_FUNC(insn)) {
> + case OPC_RISC_C_FUNC_FLDSP_LQSP:
> + if (xlen != 128) { /* C.FLDSP (RV32/64) */
> + xinsn = OPC_RISC_FLD;
> + xinsn = SET_RD(xinsn, GET_C_RD(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn));
> + }
> + break;
> + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */
> + xinsn = OPC_RISC_LW;
> + xinsn = SET_RD(xinsn, GET_C_RD(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn));
> + break;
> + case OPC_RISC_C_FUNC_FLWSP_LDSP:
> + if (xlen == 32) { /* C.FLWSP (RV32) */
> + xinsn = OPC_RISC_FLW;
> + xinsn = SET_RD(xinsn, GET_C_RD(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn));
> + } else { /* C.LDSP (RV64/RV128) */
> + xinsn = OPC_RISC_LD;
> + xinsn = SET_RD(xinsn, GET_C_RD(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn));
> + }
> + break;
> + case OPC_RISC_C_FUNC_FSDSP_SQSP:
> + if (xlen != 128) { /* C.FSDSP (RV32/64) */
> + xinsn = OPC_RISC_FSD;
> + xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn));
> + }
> + break;
> + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */
> + xinsn = OPC_RISC_SW;
> + xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn));
> + break;
> + case 7:
> + if (xlen == 32) { /* C.FSWSP (RV32) */
> + xinsn = OPC_RISC_FSW;
> + xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn));
> + } else { /* C.SDSP (RV64/RV128) */
> + xinsn = OPC_RISC_SD;
> + xinsn = SET_RS2(xinsn, GET_C_RS2(insn));
> + xinsn = SET_RS1(xinsn, 2);
> + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn));
> + }
> + break;
> + default:
> + break;
> + }
> + break;
> + default:
> + break;
> + }
I don't like that we have to manually decode the instructions. As it's
only a handful it's not the end of the world, but it seems like
duplication that could grow. Could we not use decode_insn16() instead?
That way we can share the well tested TCG decoder.
Alistair
> +
> + /*
> + * Clear Bit1 of transformed instruction to indicate that
> + * original insruction was a 16bit instruction
> + */
> + xinsn &= ~((target_ulong)0x2);
> + } else {
> + /* No need to transform 32bit (or wider) instructions */
> + xinsn = insn;
> + }
> +
> + return xinsn;
> +}
> +
> /*
> * Handle Traps
> *
> @@ -842,6 +988,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
> target_ulong deleg = async ? env->mideleg : env->medeleg;
> target_ulong tval = 0;
> + target_ulong tinst = 0;
> target_ulong htval = 0;
> target_ulong mtval2 = 0;
>
> @@ -849,20 +996,31 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> /* set tval to badaddr for traps with address information */
> switch (cause) {
> case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
> - case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
> - case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
> force_hs_execp = true;
> /* fallthrough */
> case RISCV_EXCP_INST_ADDR_MIS:
> case RISCV_EXCP_INST_ACCESS_FAULT:
> + case RISCV_EXCP_INST_PAGE_FAULT:
> + tval = env->badaddr;
> + break;
> + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
> + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
> + force_hs_execp = true;
> + /* fallthrough */
> case RISCV_EXCP_LOAD_ADDR_MIS:
> case RISCV_EXCP_STORE_AMO_ADDR_MIS:
> case RISCV_EXCP_LOAD_ACCESS_FAULT:
> case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
> - case RISCV_EXCP_INST_PAGE_FAULT:
> case RISCV_EXCP_LOAD_PAGE_FAULT:
> case RISCV_EXCP_STORE_PAGE_FAULT:
> tval = env->badaddr;
> + if (riscv_feature(env, RISCV_FEATURE_TINST)) {
> +#if defined(TARGET_RISCV32)
> + tinst = riscv_transformed_insn(env, 32, env->trap_insn);
> +#elif defined(TARGET_RISCV64)
> + tinst = riscv_transformed_insn(env, 64, env->trap_insn);
> +#endif
> + }
> break;
> case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
> case RISCV_EXCP_ILLEGAL_INST:
> @@ -955,6 +1113,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> env->sepc = env->pc;
> env->sbadaddr = tval;
> env->htval = htval;
> + env->htinst = tinst;
> env->pc = (env->stvec >> 2 << 2) +
> ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
> riscv_cpu_set_mode(env, PRV_S);
> @@ -994,6 +1153,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> env->mepc = env->pc;
> env->mbadaddr = tval;
> env->mtval2 = mtval2;
> + env->mtinst = tinst;
> env->pc = (env->mtvec >> 2 << 2) +
> ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
> riscv_cpu_set_mode(env, PRV_M);
> diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h
> index 40b6d2b64d..f4ee686c78 100644
> --- a/target/riscv/instmap.h
> +++ b/target/riscv/instmap.h
> @@ -316,6 +316,12 @@ enum {
> #define GET_RS2(inst) extract32(inst, 20, 5)
> #define GET_RD(inst) extract32(inst, 7, 5)
> #define GET_IMM(inst) sextract64(inst, 20, 12)
> +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val)
> +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val)
> +#define SET_RD(inst, val) deposit32(inst, 7, 5, val)
> +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val)
> +#define SET_S_IMM(inst, val) \
> + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5)
>
> /* RVC decoding macros */
> #define GET_C_IMM(inst) (extract32(inst, 2, 5) \
> @@ -346,6 +352,8 @@ enum {
> | (extract32(inst, 5, 1) << 6))
> #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \
> | (extract16(inst, 5, 2) << 6))
> +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst)
> +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst)
> #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \
> | (extract32(inst, 11, 1) << 4) \
> | (extract32(inst, 2, 1) << 5) \
> @@ -366,4 +374,37 @@ enum {
> #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3))
> #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3))
>
> +#define GET_C_FUNC(inst) extract32(inst, 13, 3)
> +#define GET_C_OP(inst) extract32(inst, 0, 2)
> +
> +enum {
> + /* RVC Quadrants */
> + OPC_RISC_C_OP_QUAD0 = 0x0,
> + OPC_RISC_C_OP_QUAD1 = 0x1,
> + OPC_RISC_C_OP_QUAD2 = 0x2
> +};
> +
> +enum {
> + /* RVC Quadrant 0 */
> + OPC_RISC_C_FUNC_ADDI4SPN = 0x0,
> + OPC_RISC_C_FUNC_FLD_LQ = 0x1,
> + OPC_RISC_C_FUNC_LW = 0x2,
> + OPC_RISC_C_FUNC_FLW_LD = 0x3,
> + OPC_RISC_C_FUNC_FSD_SQ = 0x5,
> + OPC_RISC_C_FUNC_SW = 0x6,
> + OPC_RISC_C_FUNC_FSW_SD = 0x7
> +};
> +
> +enum {
> + /* RVC Quadrant 2 */
> + OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0,
> + OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1,
> + OPC_RISC_C_FUNC_LWSP = 0x2,
> + OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3,
> + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4,
> + OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5,
> + OPC_RISC_C_FUNC_SWSP = 0x6,
> + OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7
> +};
> +
> #endif
> --
> 2.25.1
>
>
- Re: [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt(),
Alistair Francis <=