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[RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instruc
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From: |
frank . chang |
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Subject: |
[RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions |
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Date: |
Wed, 22 Jul 2020 17:16:19 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Remove clear function from helper function as the tail elements
are unchanged in RVV 0.9.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 39245b5ac8..fa2459d941 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4634,14 +4634,14 @@ GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8,
DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD)
/* Unsigned sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
/* Vector Single-Width Floating-Point Reduction Instructions */
#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
--
2.17.1
- [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions, (continued)
- [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions, frank . chang, 2020/07/22
- [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions, frank . chang, 2020/07/22
- [RFC v2 52/76] fpu: implement full set compare for fp16, frank . chang, 2020/07/22
- [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/07/22
- [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions, frank . chang, 2020/07/22
- [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions, frank . chang, 2020/07/22
- [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions,
frank . chang <=
- [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/22
- [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions, frank . chang, 2020/07/22
- [RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/22
- [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions, frank . chang, 2020/07/22
- [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions, frank . chang, 2020/07/22