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[RFC v2 35/76] target/riscv: rvv-0.9: iota instruction
From: |
frank . chang |
Subject: |
[RFC v2 35/76] target/riscv: rvv-0.9: iota instruction |
Date: |
Wed, 22 Jul 2020 17:15:58 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
target/riscv/vector_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 37b2582981..4560bc4379 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -578,7 +578,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111
@r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aeaf3d1cfa..c1ed0ff6ad 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4774,7 +4774,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
CPURISCVState *env, \
CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
-GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
+GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
--
2.17.1
- [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction, (continued)
- [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction, frank . chang, 2020/07/22
- [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/22
- [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/22
- [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/22
- [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/22
- [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction,
frank . chang <=
- [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/22
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, frank . chang, 2020/07/22
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22