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[RFC 65/65] target/riscv: bump to RVV 0.9
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From: |
frank . chang |
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Subject: |
[RFC 65/65] target/riscv: bump to RVV 0.9 |
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Date: |
Fri, 10 Jul 2020 18:49:19 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 8 ++++----
target/riscv/cpu.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 871c2ddfa1..6168166e64 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -340,7 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_0_09_0;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -456,8 +456,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v0.9")) {
+ vext_version = VEXT_VERSION_0_09_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -466,7 +466,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
} else {
qemu_log("vector verison is not specified, "
- "use the default value v0.7.1\n");
+ "use the default value v0.9\n");
}
set_vext_version(env, vext_version);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8b4a370572..18015f0bc0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,7 +81,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_0_09_0 0x00000900
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
--
2.17.1
- [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions, (continued)
- [RFC 29/65] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/10
- [RFC 36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions, frank . chang, 2020/07/10
- [RFC 42/65] target/riscv: rvv-0.9: single-width integer reduction instructions, frank . chang, 2020/07/10
- [RFC 46/65] target/riscv: rvv-0.9: slide instructions, frank . chang, 2020/07/10
- [RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions, frank . chang, 2020/07/10
- [RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions, frank . chang, 2020/07/10
- [RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction, frank . chang, 2020/07/10
- [RFC 53/65] target/riscv: rvv-0.9: single-width scaling shift instructions, frank . chang, 2020/07/10
- [RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert, frank . chang, 2020/07/10
- [RFC 65/65] target/riscv: bump to RVV 0.9,
frank . chang <=
- [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/10
- [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags, frank . chang, 2020/07/10
- [RFC 16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/10
- [RFC 23/65] target/riscv: rvv-0.9: floating-point classify instructions, frank . chang, 2020/07/10
- [RFC 24/65] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/10
- [RFC 26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/10
- [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/10