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[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instructio
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From: |
frank . chang |
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Subject: |
[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction |
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Date: |
Fri, 10 Jul 2020 18:48:36 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e3f0fba912..1d34fa647b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -509,7 +509,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
- Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, (continued)
[RFC 09/65] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/10
[RFC 13/65] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/10
[RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
[RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
[RFC 21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation, frank . chang, 2020/07/10
[RFC 22/65] target/riscv: rvv-0.9: floating-point square-root instruction,
frank . chang <=
[RFC 28/65] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/10
[RFC 32/65] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/10
[RFC 33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/10
[RFC 35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions, frank . chang, 2020/07/10
[RFC 38/65] target/riscv: rvv-0.9: integer merge and move instructions, frank . chang, 2020/07/10
[RFC 39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions, frank . chang, 2020/07/10
[RFC 40/65] target/riscv: rvv-0.9: integer comparison instructions, frank . chang, 2020/07/10
[RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions, frank . chang, 2020/07/10
[RFC 50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions, frank . chang, 2020/07/10
[RFC 54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add, frank . chang, 2020/07/10