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[PATCH v1 8/9] riscv/opentitan: Connect the UART device
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 8/9] riscv/opentitan: Connect the UART device |
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Date: |
Sat, 25 Apr 2020 04:29:29 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/opentitan.c | 24 ++++++++++++++++++++++--
include/hw/riscv/opentitan.h | 13 +++++++++++++
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 3a845fbb7b..81cd835e8b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -96,6 +96,9 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
sysbus_init_child_obj(obj, "plic", &s->plic,
sizeof(s->plic), TYPE_IBEX_PLIC);
+
+ sysbus_init_child_obj(obj, "uart", &s->uart,
+ sizeof(s->uart), TYPE_IBEX_UART);
}
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -137,8 +140,25 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, memmap[IBEX_PLIC].base);
- create_unimplemented_device("riscv.lowrisc.ibex.uart",
- memmap[IBEX_UART].base, memmap[IBEX_UART].size);
+ /* UART */
+ dev = DEVICE(&(s->uart));
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
+ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, memmap[IBEX_UART].base);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_TX_WATERMARK_IRQ));
+ sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_RX_WATERMARK_IRQ));
+ sysbus_connect_irq(busdev, 2, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_TX_EMPTY_IRQ));
+ sysbus_connect_irq(busdev, 3, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_UART_RX_OVERFLOW_IRQ));
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 8d6a09b696..825a3610bc 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
+#include "hw/char/ibex_uart.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
#define RISCV_IBEX_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct LowRISCIbexSoCState {
/*< public >*/
RISCVHartArrayState cpus;
IbexPlicState plic;
+ IbexUartState uart;
MemoryRegion flash_mem;
MemoryRegion rom;
@@ -63,4 +65,15 @@ enum {
IBEX_USBDEV,
};
+enum {
+ IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
+ IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
+ IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
+ IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
+ IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
+ IBEX_UART_TX_EMPTY_IRQ = 0x23,
+ IBEX_UART_RX_WATERMARK_IRQ = 0x22,
+ IBEX_UART_TX_WATERMARK_IRQ = 0x21
+};
+
#endif
--
2.26.2
- [PATCH v1 0/9] RISC-V Add the OpenTitan Machine, Alistair Francis, 2020/04/26
- [PATCH v1 1/9] riscv/boot: Add a missing header include, Alistair Francis, 2020/04/26
- [PATCH v1 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/04/26
- [PATCH v1 3/9] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/04/26
- [PATCH v1 5/9] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/04/26
- [PATCH v1 4/9] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/04/26
- [PATCH v1 8/9] riscv/opentitan: Connect the UART device,
Alistair Francis <=
- [PATCH v1 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/04/26
- [PATCH v1 9/9] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/04/26
- [PATCH v1 7/9] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/04/26