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[PATCH v1 01/15] target/riscv: Set access as data_load when validating s
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 01/15] target/riscv: Set access as data_load when validating stage-2 PTEs |
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Date: |
Sun, 26 Apr 2020 09:19:13 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bc80aa87cf..ed64190386 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -456,7 +456,7 @@ restart:
hwaddr vbase;
/* Do the second stage translation on the base PTE address. */
- get_physical_address(env, &vbase, &vbase_prot, base, access_type,
+ get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
mmu_idx, false, true);
pte_addr = vbase + idx * ptesize;
--
2.26.2
- [PATCH v1 00/15] RISC-V: Update the Hypervisor spec to v0.6, Alistair Francis, 2020/04/26
- [PATCH v1 02/15] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/04/26
- [PATCH v1 01/15] target/riscv: Set access as data_load when validating stage-2 PTEs,
Alistair Francis <=
- [PATCH v1 03/15] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/04/26
- [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/04/26
- [PATCH v1 04/15] target/riscv: Implement checks for hfence, Alistair Francis, 2020/04/26
- [PATCH v1 06/15] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 07/15] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/04/26
- [PATCH v1 08/15] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/04/26
- [PATCH v1 09/15] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/04/26
- [PATCH v1 10/15] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/04/26
- [PATCH v1 12/15] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/04/26
- [PATCH v1 13/15] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/04/26