|
From: | Jonathan Behrens |
Subject: | Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren |
Date: | Tue, 21 Jan 2020 08:05:23 -0500 |
On Wed, 14 Aug 2019 20:19:39 PDT (-0700), address@hidden wrote:
> Ping! What is the status of this patch?
Sorry, I must have lost track of it. I've added it to my patch queue.
>
> On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens <address@hidden>
> wrote:
>
>> Bin, that proposal proved to be somewhat more controversial than I was
>> expecting, since it was different than how currently available hardware
>> worked. This option seemed much more likely to be accepted in the short
>> term.
>>
>> Jonathan
>>
>> On Mon, Jul 1, 2019 at 9:26 PM Bin Meng <address@hidden> wrote:
>>
>>> On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis <address@hidden>
>>> wrote:
>>> >
>>> > On Mon, Jul 1, 2019 at 8:56 AM <address@hidden> wrote:
>>> > >
>>> > > From: Jonathan Behrens <address@hidden>
>>> > >
>>> > > QEMU currently always triggers an illegal instruction exception when
>>> > > code attempts to read the time CSR. This is valid behavor, but only if
>>> > > the TM bit in mcounteren is hardwired to zero. This change also
>>> > > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
>>> > > and 64-bit targets.
>>> > >
>>> > > Signed-off-by: Jonathan Behrens <address@hidden>
>>> >
>>> > Reviewed-by: Alistair Francis <address@hidden>
>>> >
>>>
>>> I am a little bit lost here. I think we agreed to allow directly read
>>> to time CSR when mcounteren.TM is set, no?
>>>
>>> Regards,
>>> Bin
>>>
>>
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